For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Maintaining mobility improvement and short channel control as microelectronic device dimensions scale past the 15 nanometer (nm) node provides a challenge in device fabrication. Nanowires used to fabricate devices provide improved short channel control. For example, silicon germanium (SixGe1-x) nanowire channel structures (where x<0.5) provide mobility enhancement at respectable Eg, which is suitable for use in many conventional products which utilize higher voltage operation. Furthermore, silicon germanium (SixGe1-x) nanowire channels (where x>0.5) provide mobility enhanced at lower Egs (suitable for low voltage products in the mobile/handheld domain, for example.
Many different techniques have been attempted to improve external resistance (Rext) of transistors including improved contact metals, increased activation of dopant and lowered barriers between the semiconductor and contact metal. However, significant improvements are still needed in the area of Rext reduction.